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| Traffic Light at Junction |
Let Us Go To The Logic Of The Project:
Logic Is More Important Than Code.
Four Roads So Four Traffic Light:
1st traffic light is n_lights ( north direction light)
2nd traffic light is e_lights ( east direction light)
3rd traffic light is s_lights ( south direction light)
4th traffic light is w_lights ( west direction light)
For n_lights:
conditions:
I am going 3bit
if 001 - GREEN
010 - YELLOW
100 - RED
For e_lights:
conditions:
I am going 3bit
if 001 - GREEN
010 - YELLOW
100 - RED
For s_lights:
if 001 - GREEN
010 - YELLOW
100 - RED
For w_lights:
if 001 - GREEN
010 - YELLOW
100 - RED
conditions:
I am going 3 bit so counter = 3'b 111
why 3 bit ? why not 4 or 2 bit?
In 3 bit I have 8 different combination of 1's and 0's
(000,001,010,011,100,101,110,111)
In verilog code you can see I have used only 8 parameter
each parameter i have assign one 3bit values
parameter [2:0] n_g = 3'b000;
parameter[ 2:0]n_y = 3'b001;
parameter [2:0]s_g = 3'b010;
parameter [2:0]s_y= 3'b011;
parameter [2:0]e_g= 3'b100;
parameter [2:0]e_y= 3'b101;
parameter [2:0]w_g= 3'b110;
parameter [2:0]w_y= 3'b111
so you can use 4 , 5, 6 bit 😁😀😀😀
but the problem is size will increase 😐 (not length of code)
length will be more or less same.
3 bit of 1's and 0 's size is 8 bit
so 6 bit of 1's and 0 's size is 2 power 6 is 64 bit
In binary there is only 2 bit (0,1) 2 ^ 3 (2 power 3) is 8
so ranges is 0 to 7
Truth table has total 8 (0 to 7)
is 000,001,010,011,100,101,110,111
North light Condition (GREEN )
if north traffic light is in green all other light should be in red
let's represent in above statement in binary form:
if n_lights = 001
e_lights = 100
s_lights = 100
w_lights = 100
North light Condition (YELLOW)
if north traffic light is in YELLOWall other light should be in RED
let's represent in above statement in binary form:
if n_lights = 010
e_lights = 100
s_lights = 100
w_lights = 100
like wise Same logic for other lights
Main Module Code is:
module
traffic_control(n_lights,s_lights,e_lights,w_lights,clk,rst_a);
output reg [2:0]
n_lights,s_lights,e_lights,w_lights;
input
clk;
input
rst_a;
reg [2:0] state;
parameter [2:0] north=3'b000;
parameter [2:0] north_y=3'b001;
parameter [2:0] south=3'b010;
parameter [2:0] south_y=3'b011;
parameter [2:0] east=3'b100;
parameter [2:0] east_y=3'b101;
parameter [2:0] west=3'b110;
parameter [2:0] west_y=3'b111;
reg [2:0] count;
always @(posedge clk, posedge rst_a)
begin
if (rst_a)
begin
state=north;
count =3'b000;
end
else
begin
case (state)
north :
begin
if (count==3'b111)
begin
count=3'b000;
state=north_y;
end
else
begin
count=count+3'b001;
state=north;
end
end
north_y :
begin
if (count==3'b011)
begin
count=3'b000;
state=south;
end
else
begin
count=count+3'b001;
state=north_y;
end
end
south :
begin
if (count==3'b111)
begin
count=3'b0;
state=south_y;
end
else
begin
count=count+3'b001;
state=south;
end
end
south_y :
begin
if (count==3'b011)
begin
count=3'b0;
state=east;
end
else
begin
count=count+3'b001;
state=south_y;
end
end
east :
begin
if (count==3'b111)
begin
count=3'b0;
state=east_y;
end
else
begin
count=count+3'b001;
state=east;
end
end
east_y :
begin
if (count==3'b011)
begin
count=3'b0;
state=west;
end
else
begin
count=count+3'b001;
state=east_y;
end
end
west :
begin
if (count==3'b111)
begin
state=west_y;
count=3'b0;
end
else
begin
count=count+3'b001;
state=west;
end
end
west_y :
begin
if (count==3'b011)
begin
state=north;
count=3'b0;
end
else
begin
count=count+3'b001;
state=west_y;
end
end
endcase // case (state)
end // always @ (state)
end
always @(state)
begin
case (state)
north :
begin
n_lights = 3'b001;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: north
north_y :
begin
n_lights = 3'b010;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: north_y
south :
begin
n_lights = 3'b100;
s_lights = 3'b001;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: south
south_y :
begin
n_lights = 3'b100;
s_lights = 3'b010;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: south_y
west :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b001;
end // case: west
west_y :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b010;
end // case: west_y
east :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b001;
w_lights = 3'b100;
end // case: east
east_y :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b010;
w_lights = 3'b100;
end // case: east_y
endcase // case (state)
end // always @ (state)
endmodule
TestBench:
module traffic_control_tb;
wire [2:0]
n_lights,s_lights,e_lights,w_lights;
reg clk,rst_a;
traffic_control DUT
(n_lights,s_lights,e_lights,w_lights,clk,rst_a);
initial
begin
clk=1'b1;
forever #5 clk=~clk;
end
initial
begin
rst_a=1'b1;
#15;
rst_a=1'b0;
#1000;
$stop;
end
endmodule
So, This is the output of Traffic light using verilog
I have Used XILINUX Software called VIVADO
To Create project in vivado Click here
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