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Showing posts from April, 2021

Density based traffic signal system using image processing

Contact Me for Project Prize Mail Id:  tamilblogelectronic@gmail.com Measure Traffic density and ambulance detection in Realtime project. What We Do in This Project: (Both Software & Hardware Project Available) ( i) Traffic Density Measure - Realtime (Means using Traffic Camera or Traffic Video) First,  we do Vehicle Detection in Video/Camera using Image Processing. Second, we Count the Vehicle We Detected in Video/Camera using Image Processing. Third, We Compare Two lane Vehicle Density in Video/Camera , if lane detect more no. of vehicle will be Prioritized first.   (ii) Ambulance Detection in Single Lane  - Realtime (Means using Traffic Camera or Traffic Video) : First, We Collect the Images of Ambulance. Second, we train our Image model using sample ambulance image. using Yolo image Model, we able to Detect the Ambulance in Video/ Camera. (iii) Ambulance Detection in Multiple Lane  - Realtime (Means using Traffic Camera or Traffic Vid...

boost::filesystem::remove: The process cannot access the file because it is being used by another process in VIVADO (XILINUX)

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( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com And other social media for Soft copies of any Book.   Final Year Engineering Project ( both Hardware and Software Project) :   Density Based Traffic control for Smart Ambulance System using Image Processing    Click Here   - Electronics Project Ambulance Detection Project In Vivado If You Run A Program With Both Main Module And Test Bench And You Try To Run Other Program In the Same Project Will You Will Get This Error  boost::filesystem::remove: The process cannot access the file because it is being used by another process in VIVADO If You Try To Run A Different Code In Same Project (I.e First You Tried Is Full Adder Second You Try To Run A Half Adder Or Any Thing With Correct Code(I.e Without Error In That Code) ) You May Get An Error As  boost::filesystem::remove: The process cannot access the file because it is being ...

Verilog Project

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( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com  And other social media for Soft copies of any Book. Traffic Light at Junction Let Us Go To The Logic Of The Project:  Logic Is More Important Than Code. Four Roads So Four Traffic Light: 1st traffic light is n_lights ( north direction light) 2nd  traffic light is e_lights   ( east direction light) 3rd  traffic light is s_lights   ( south direction light) 4th  traffic light is w_lights  ( west direction light) For n_lights: conditions: I am going 3bit  if 001 - GREEN     010 - YELLOW    100 - RED  For e_lights: conditions: I am going 3bit  if 001 -  GREEN     010 -  YELLOW    100 -  RED  For s_lights: if 001 -  GREEN     010 -  YELLOW    100 -  RED  For w_lights: if 001...

what is sin cos tan in trigonometry

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   ( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com And other social media for Soft copies of any Book. What is Sin wave? Sine wave is wave is discovered by Joseph Fourier Especially Engineering Student Should Know What is Fourier? 🙂 In Wave "Phase" Means Angle. Why We Shouldn't Call Phase As Angle?  If  We Called Angle It Will Be Ordinary Term . If We Called Phase It Indicates The Wave .  

AMAZON BOOKS MY RECOMMENDATION:

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AMAZON BOOKS RECOMMENDATION  by TAMIL BLOG Electronics : If you have any Queries follow me on Quora https://tamilblogelectronics.quora.com/  

HOW TO CREATE PROJECT IN VIVADO (XILINUX) AND TEST BENCH

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      ( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com  And other social media for Soft copies of any Book.   AFTER INSTALL XILINUX  STEP 1 :CLICK ICON TO OPEN STEP 2: AFTER ITS OPENED THE SCREEN WILL BE LIKE THIS  STEP 3 : CLICK CREATE PROJECT AFTER YOU CLICKED CREATE PROJECT WILL BE LIKE THIS BELOW IMAGE: AFTER CREATE PROJECT CLICK NEXT THIS TAB WILL SHOW CLICK PROJECT NAME AND NAME THE PROJECT AND CLICK NEXT AFTER CLICK NEXT THIS TAB WILL SHOW CHOOSE RTL PROJECT AND CLICK NEXT CLICK CREATE FILE TO ADD SOURCE NAME AND TYPE SOURCE NAME AS LIKE GATE MODELLING MEANS    (gate_dff )  dff means d flipflop AFTER NAMED SOURCE WILL BE LIKE THIS CLICK NEXT CLICK NEXT THIS IS VERY IMPORTANT  CATEGORY : GENERAL PURPOSE PACKAGE : fb 484 SPEED : -1 FAMILY : KINTEX 7 AFTER YOU DID PREVIOUS STEPS ONLY TWO ROW WILL  BE THERE IN BOTTOM BOX.   CLICK ANY ...

Verilog and its types

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              ( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com And other social media for Soft copies of any Book.                 What is Verilog HDL? Its a Hard Description language (HDL) its a high level language to describe the circuit by syntax and sentences its is similar other computer software languages like C++,  Verilog is hardware language like circuits with transistor or switch  level, gate level. Who developed Verilog? Verilog is developed by gateway design automation for logic simulation in 1984   Verilog HDL: Its allow you to simulate earlier in design cycle of circuit you design in order to correct errors or experiment in different architectures HDL is usually more readable to design when large circuit is designed  Its has 4 level of abstraction ( abstractions means    si...

what is noise and its types in communication?

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( Note :   Click Label To Check various Topics like Diodes,Rectifier,etc.) Contact   tamilblogelectronic@gmail.com And other social media for Soft copies of any Book. What is  NOISE ?  Noise is the disturbance . • It is an unwanted signal that corrupts the desired message signal.  • Electrical Noise is an unwanted signal that appears along with the Desired Electrical Signal and falls within the same frequency band as that of message signal.  • Noise signals are random signals. They are non-deterministic in nature.  • The desired deterministic signals can be modeled mathematically.  • However the non-deterministic signals must be studied completely so that they can also be represented mathematically.  • The noise gets added with the signal as shown below: Categories of Noise •  Correlated – this noise the one which is present whenever message signal is present.  • Uncorrelated – this noise is the one which is present even i...

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boost::filesystem::remove: The process cannot access the file because it is being used by another process in VIVADO (XILINUX)

Verilog Project

HOW TO CREATE PROJECT IN VIVADO (XILINUX) AND TEST BENCH

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